Intel today has a few reasons for celebration, and we’ll be tackling all of those in this article. To help kick the day off, CEO Paul Otellini announced that the company would be investing a total of $7 billion dollars over the course of the next two years to help upgrade existing fabs to pave the way for 32nm development. Intel believes that this move will help create up to 7,000 new jobs, all of which will be in the United States – a point that Intel clearly likes to stress.
That announcement was a precursor to a media briefing that was held this afternoon, where all of the focus was directed towards the company’s “Tick” phase. As a quick recap, Intel abides by a Tick/Tock methodology, where the Tock is a brand-new micro-architecture, such as Nehalem, while Tick is a revision, which, up to now, has always involved a brand-new process.
As we’ve known for a while, Intel’s first 32nm processors are known as Westmere, which is a follow-up to Nehalem. However, there’s a lot more to Westmere than just a die shrink, as Intel has made numerous changes to the architecture. No joke. Intel has either changed or added so much here, that Westmere could almost be considered to be a “Tock” phase. But, Westmere isn’t really a brand new micro-architecture, but rather a revision to Nehalem, with many features tacked-on.
One of the main pieces of information most people are going to look for out of a media briefing like this is the roadmap update, and that’s one thing we got. Although most of the talk was about Westmere, we’re still far from done with the 45nm offerings, and many more are en route. Take the Lynnfield desktop chip, for example, which is likely to come out as Core i5, and also the mobile counterpart Clarksfield. Both of these chips will be Quad-Cores that feature 8 threads, just like Nehalem. Imagine that… eight threads on a notebook. Insane.
Both the desktop Lynnfield (LGA-1156) and mobile Clarksfield (mPGA-989) will become available sometime this year, with the 32nm parts to come later. What’s most notable about the 32nm parts though, is the fact that initial models will deliver both a GPU and CPU inside of the same processor.
This is an area where we have to divulge a little more information, because this progression is far too important to just skip through. When launched, Intel will likely become the first to offer a GPU + CPU in one package, the result of which should be IGP graphics performance that is unparallelled to anything before it. It’s really hard to conclude on that thinking without testing the processor out for ourselves, but placing a GPU so close to the CPU has got to be something that brings noticeable benefit.
The major changes don’t end there, however… even our motherboards will undergo some alteration. Because of the die shrink, and the move of the memory controller onto the CPU, various components have been shifted around, and as a result, the Southbridge has been removed entirely. The slide shown below gives an example of the new “2-Chip Solution”.
Because “Core i5″ will include an integrated graphics chip (at least on initial models), the PCI-E interface is now part of the CPU, rather than the Northbridge. The display interface will still remain on the Northbridge, however, but the Clock Buffer, which is normally found on a Southbridge, will move right in. Essentially, we are moving from three chips to two, which is a substantial move in my opinion.
In the following slide, you can get a better idea of how the GPU and CPU will sit on the same substrate. Rather than sit in the direct middle like previous processors have, the GPU/IMC chip will sit to the left while the CPU sits to the right. It’s interesting to note that while the CPU will be produced at 32nm, the GPU will be produced at 45nm. That’s still a decrease in die size from the current 65nm offerings. It could be that once the GPU does become 32nm, the two dies will be merged, but something tells me that such a design is going to take a little more work than keeping the two chips separate.
Past those features, both Clarkdale and Arrandale will launch as Dual-Core processors, but will follow along in Nehalem’s footsteps by offering twice as many threads. So for a given Clarkdale chip, for example, you can expect to see a Dual-Core model with 4 threads and a GPU all inside of a single chip. Other features include 4MB of L3 Cache (on par with the Cache/Core ratio of Core i7), an integrated memory controller and of course, Turbo Boost and Hyper-Threading technologies.
Unlike Core i7, however, mainstream desktop/mobile Westmere chips will not feature a QPI bus or a triple-channel memory controller. Rather, we’ll revert to a dual-channel controller and have no QPI clock to worry about (what new factors will come into overclocking is yet to be seen).
Although it wasn’t unexpected, the first enthusiast Westmere part, slated for early 2010 release, will be a Hexa-Core chip, rather than Quad-Core like the last few major launches have been. Because these chips still include everything that made Core i7 notable, and doesn’t require an iGPU (high-end users are not going to want an integrated GPU), the upcoming model will be fully compatible with the X58 chipset. This is a nice point to note, as it should mean that upgrading to the Westmere at the time won’t result in requiring a new motherboard. Also, like current i7 chips, the first Westmere enthusiast offering will deliver 12 threads of execution.
On the enterprise side of things, 32nm Xeon’s will come months after the initial desktop chips are released. Although it’s difficult to understand their time-line, Intel shows that both the Tylersburg-EP and Foxhollow platforms will experience 32nm first, with the entry-level 3000 series to likely come first. On the top-end, the multi-CPU Boxboro-EX platform will see processors released in the second half of 2010.
Security Instructions & Final Thoughts
One of the most notable feature additions to Westmere is the introduction seven brand-new security-related instructions, six of which are dedicated for AES encryption and decryption, with the other being devoted to carry-less multiplication (PCLMULQDQ), which will allow the processor to multiply two 64-bit operands without generating carries.
On the AES side of things, the addition of such instructions will be most appreciated, given that a sheer number of security-related applications utilize the algorithms. One example given would be full-disk encryption. As we found out a few weeks ago, some disk manufacturers are aiming towards developing drives that automatically encrypt your data, in either AES128 or AES256. With these new instructions, though, such encryption could be available on all drives… not only ones to ship with the feature, with minimal or no performance loss.
As a closing statement, I have to say that today’s announcements are quite impressive. Even though a lot of what we’ve learned about today has been rumored or planned for a while, it was great to get a solid update that exposed so much information, and because of that, we can have a much better grasp on what to expect from Intel later this year and into next.
Personally, I’m most looking forward to the 32nm desktop and mobile chips. The ability to have four threads available and an integrated GPU sounds like a great deal to me. When released, it should be easier than ever to build a very small PC that’s still capable. Intel’s integrated graphics haven’t been all-too-impressive in the past where performance is concerned, but with a pairing of the CPU and GPU on the same substrate, we might see performance that blows past all of the competition.
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