Intel Provides Details On New Products…

INTEL DEVELOPER FORUM, Beijing, April 17, 2007 — Intel Corporation executives today detailed more than 20 new products, technology innovations and industry initiatives — many of them industry firsts — aimed at making the World Wide Web, computers and consumer electronics devices much more responsive, friendlier and secure.

Under the backdrop of Intel’s leadership in 45nm Hi-k metal gate silicon technology and how it will ignite new innovation and growth opportunities, Intel executives at the Intel Developer Forum disclosed new performance details for its next-generation “Penryn” processor family. The company also unveiled two product roadmaps for Intel architecture (IA)-based System on Chip (SOC) consumer electronic (CE) devices and business uses.

“Welcome to the era of multicore, an era in which all of our computing capabilities will multiply our own personal capabilities,” said Justin R. Rattner, Intel’s chief technology officer. “This Beijing developer forum will show how our multiple innovations go hand in hand with evolutions in social networking, PC and TV entertainment, online commerce and other growing demands on the Internet. Today, Intel is delivering a breadth of multicore processors worldwide and a product roadmap providing the incredible performance boost and energy efficiency needed to put the consumer more in control of the information age.”

The IDF is being held for the first time in Beijing. Last month, Intel announced plans to invest $2.5 billion to build China’s first 300mm wafer fabrication facility in the city of Dalian.

Multicore Performance Era, Core Microarchitecture
Gelsinger provided performance indicators for Intel’s upcoming Penryn family of processors. For desktop PCs, he said to expect increases of about 15 percent for imaging-related applications; 25 percent for 3-D rendering; more than 40 percent for gaming; and more than 40 percent faster video encoding with Intel SSE4 optimized video encoders. The indicators were based on pre-production 45nm Hi-k Intel(R) quad core processor running at 3.33 Gigahertz (GHz) with a 1333 Megahertz (MHz) front side bus (FSB) and 12MB cache versus an Intel(R) Core(TM) 2 Extreme processor QX6800 introduced last week at 2.93 GHz with 1066 FSB and 8MB cache.

For high-performance computing (HPC) and workstation systems, Gelsinger said to expect gains up to an estimated 45 percent for bandwidth intensive applications; and a 25 percent increase for servers using Java*. These indicators were derived from pre-production 45nm Hi-k Intel(R) Xeon(R) processors with 1600 MHz front side bus for workstation and HPC, and a 1333 MHz front side bus for servers versus today’s quad-core Intel(R) Xeon(R) X5355 processors.

Gelsinger said that Intel has begun planning products based on a highly parallel, IA-based programmable architecture codenamed “Larrabee.” It will be easily programmable using many existing software tools, and designed to scale to trillions of floating point operations per second (Teraflops) of performance. The Larrabee architecture will include enhancements to accelerate applications such as scientific computing, recognition, mining, synthesis, visualization, financial analytics and health applications.

The company also has plans for Intel(R) QuickAssist Technology – a comprehensive initiative to optimize the use of accelerators in servers. Accelerators increase the performance of a single function, like security encryption or financial computation, while reducing power consumption. This initiative includes support for acceleration using IA-based multi-core processors and third party accelerators working together in Intel-based servers, and developing new integrated accelerators inside the IA-based processor itself.

Gelsinger unveiled “Tolapai” plans, the first in what will be a family of enterprise-class “system-on-chip” (SoC) products that integrate several key system components into a single Intel architecture-based processor. The 2008 Tolapai product is expected to reduce the chip sizes by up to 45 percent and power consumption by approximately 20 percent compared to a standard four-chip design1, while improving throughput performance and processor efficiency. Tolapai will include the new Intel(R) QuickAssist Integrated Accelerator technology.

Gelsinger also outlined product plans, including one for Intel’s high-end multi-processor servers (codenamed “Caneland”). The quad- and dual-core Intel(R) Xeon(R) processor 7300 series will arrive in the third quarter in 80- and 50-watt versions for blades. The new servers will complete the company’s transition to its Intel(R) Core(TM) microarchitecture for Xeon processors. Sun Microsystems demonstrated its Solaris operating system running on an Intel Xeon(R) 5100 series processor based system using Intel Dynamic Power technology, a new capability focused on reducing the power required for a memory subsystem.

Further bolstering PC security and manageability benefits, Intel will introduce the next-generation Intel(R) vPro(TM) processor technology, codenamed “Weybridge,” in the second half of the year and using the new Intel(R) 3 Series Chipset family, formerly codenamed “Bear Lake.”

This will follow the launch of Intel(R) Centrino(TM) Pro processor technology, bringing the business-centric features of vPro systems to notebooks for the first time.

Finally, Microsoft demonstrated Windows* Server code name “Longhorn” and two complementary technologies: Windows Server Core, and its new hypervisor-based virtualization solution, Windows Server virtualization, running on the Intel quad-core Xeon processors. The integrated platform combination, demonstrates running up to 8 core virtual machines, with “hot add” features, delivering increased efficiency and uptime for IT managers.

Home PCs, Consumer Electronics Innovation
Also at IDF, Eric Kim, senior vice president and general manager of Intel’s Digital Home Group, said Intel is focused on developing products and technologies that provide consumers with greater control, choice, clarity and community – the “4C’s” – across computers and CE platforms spanning PCs, laptops, televisions, set-top-boxes and other networked media players.

Kim detailed Intel’s strategy to deliver a common, unified IA-based processor foundation across PC and CE platforms. He said the Intel(R) CE 2110 Media Processor, a system-on-a-chip (SoC) architecture for CE devices will help manufacturers accelerate time to market for smarter, more cost-effective designs that provide necessary performance, flexibility and headroom. Kim said the company will deliver its first CE-optimized IA-based SoC in 2008.

Intel also plans to deliver a number of desktop computer products later this year, including updates to its Intel(R) Viiv(TM) processor technology roadmap, and a new high-end enthusiast and gaming platform codenamed “Skulltrail.”

Future generations of Intel Viiv processor technology will be based on the Intel(R) 3 Series Chipset family arriving this quarter and delivering improved graphics support with features such as enhanced Intel(R) Clear Video Technology and hardware support for Microsoft* DX10 for smoother high-definition playback and 3D visuals. Intel 3 Series Chipsets also boost system performance with a faster 1333 MHz front side bus and support for DDR3 memory, PCI Express* 2.0 and Intel(R) Turbo Memory for application acceleration and faster boot times.

Intel R&D Sets Course For Innovation
In his opening address, Rattner reiterated the company’s goals for processor performance and energy efficiency noting that Intel will be able to drive down power consumption by a factor of 10 for the ultra mobile computing segment by 2010. Intel will also create future processors at Teraflops speeds, and Rattner urged the industry to work together to take advantage of this raw processing power. The next stage of Intel’s tera-scale research will be around “stacked” memory on top of the 80-core research chip Intel demonstrated earlier this year.